This invention relates to bubble memory systems that are comprised of multiple bubble memory chips each of which have some defective minor loops. Various architectures for bubble memory chips have been described in the prior art. Presently, one of the most popular designs includes a plurality of minor loops that are loaded in a serial-parallel fashion and are unloaded in a parallel-serial fashion. A bubble generator couples to the serial portion of the serial-parallel path and generates bubbles thereon. The generated bubbles propagate along serial protion of the path to align with respective minor loops. Then the bubbles are transferred to the parallel paths to each of the minor loops. Also a bubble detector connects to the serial portion of the parallel-serial path from the loops. Bubbles are first transferred in parallel to the serial portion of the path. Then they are serially propagated to the generator for detection.
It has been found desirable in the prior art to include extra or redundant minor loops on the chips. This is because, due to various fabrication deficiencies, a small percentage of the loops may become defective. Typically, this is about eight percent. By adding redundant loops, a predetermined portion of the total number of loops can be guaranteed to be non-defective. Thus, the redundant loops improve chip yield.
A problem however, with adding redundant loops on the memory chips is that some control circuitry is required for use in conjunction with the chips to insure that no information bits are loaded into or read from the defective loops. In other words, information words to be loaded into the memory must somehow be "scrambled" such that none of the bubbles on the serial portion of the serial-parallel path align with defective minor loops when the transfer of bubbles into the loops is made. The control circuitry must also somehow perform the inverse operation of "unscrambling" the signals from the bubble detector such that the original data words are reconstructed.
One way to perform this "scrambling" and "unscrambling" operation is to utilize a random access memory (RAM) as a buffer to the bubble memory. In a write operation, the data words are first written into the RAM. There, the words are modified or scrambled by inserting zeros between those bits of the words which would otherwise align with a defective minor loop in the bubble memory chips. Then the scrambled information is written into the bubble memory. Similarly, during a read operation, all of the signals from the bubble detectors are stored in the RAM. Then this information is unscrambled by first deleting those bits which came from defective minor loops. The remaining bits are then realigned to eliminate holes between the bits.
This apparatus however, has several undesirable features. For example, it requires the addition of considerable random access memory which is cost prohibitive. Also it requires substantial time to modify the data in the RAM before it is loaded into the bubble memory chips, and to modify the data in the RAM after it is read from the bubble memory chips. As a result, this system is both undesirably expensive and slow in operation.
Therefore, it is one object of the invention to provide an improved bubble memory system.
Still another object of the invention, is to provide a bubble memory system that utilizes an improved FIFO device to make defective minor loops transparent to the user.